The present invention relates to digital data Manchester decoding system, and more particularly to a decoder which requires a reduced oversampling rate and reduced hardware complexity in comparison to conventional Manchester decoders.
Manchester encoding is a well known encoding technique, wherein there is a mid-bit transition from the "1" state to the "0" state, or vice versa, in the center of each bit cell. It is the direction of this transition that distinguishes a "1" from a "0".
Conventional devices for Manchester decoding have typically required a oversampling rate of at least sixteen times the data rate, and have been relatively hardware intensive. This results in relatively high power consumption rates, which can be especially disadvantageous for battery-powered circuits.
It is therefore an object of this invention to provide a Manchester decoder which employs a minimized sample rate and reduced hardware and thereby enjoys relatively low power consumption rates.
A further object of the invention is to provide a Manchester decoder circuit which will provide a system clock synchronized to the incoming data.